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Table 5-3: SDI Audio Extract Register Map

NameBytes Offset

Audio Control Register00h

Audio Presence Register01h

Audio Status Register02h

SD EDP Presence Register03h

Error Status Register04h

Reserved05h

FIFO Status Register06h

Clock Status Register07h

Reserved08h-09h

Channel Status RAM (0×00), (0×01), ... (0×2F)10h-3Fh

Table 5-4: SDI Audio Extract Registers

DescriptionAccessNameBit

Audio Control Register

Enables the audio extraction component and internal AES

output.

RWEnable0

Defines the audio pair that the component extracts. For

example:

• [000] = Extract the first channel pair of audio signal

• [111] = Extract the eighth channel pair of audio signal

RWExtract pair3:1

For 3G-SDI Level A standard, this field extends the extract

pair field to allow for future implementations with 32

embedded audio channels.

For 3G-SDI Level B standard, this field selects the active

video half of the 3G multiplex.

RWExtract pair MSB4

Drive this register high to mute the audio output.RWMute5

Reserved for future use.—Unused7:6

Altera Corporation

SDI Audio IP Registers

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SDI Audio Extract Registers

UG-SDI-AUD

2014.06.30

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AudioControl Avalon Betriebsanweisung Seite 36